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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2005, zarlink semiconductor inc. all rights reserved. features ? meets requirements of gr-253-core for sonet stratum 3 and sonet minimum clock ? meets requirements of gr-1244-core stratum 3 ? meets requirements of g.813 option 1 and option 2 for sdh equipment clocks (sec) with external jitter attenuator ? provides oc-3/stm-1, ds3, e3, 19.44 mhz, ds2, e1, t1, 8 khz and st-bus clock outputs ? accepts reference inputs from two independent sources ? selectable 1.544 mhz, 2.048 mhz, 19.44 mhz or 8khz input reference frequencies ? holdover accuracy of 0.02 ppm ? adjustable output clock phase supporting master- slave arrangements ? hardware or microprocessor control (8 bit microprocessor interface) ? 3.3 v supply ? jtag boundary scan applications ? sonet/sdh add/drop multiplexers ? sonet/sdh uplinks ? integrated access devices ? atm edge switches description the MT90401 is a digital phase locked loop (dpll) that is designed to synchronize sdh (synchronous digital hierarchy) and sonet (synchronous optical network) networking equipment. the MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by telcordia, ansi and the itu during normal operation and in the presence of disturbances on the incomi ng synchronization signals. january 2005 ordering information MT90401ab 80 pin lqfp trays MT90401ab1 80 pin lqfp* trays *pb free matte tin -40 c to +85 c MT90401 sonet/sdh system synchronizer data sheet figure 1 - functional block diagram virtual reference selected refer- ence ieee 1149.1a reference select feedback tie corrector enable control state machine dpll state select state select frequency select mux input impairment monitor output interface circuit reference select mux tie corrector circuit ms1 ms2 fs1 fs2 tck sec rst rsel vdd vss tclr c1.5o c19o c2o c4o c8o c16o c44/c34 f0o f8o tdo tdi tms trst c6o holdover flock lock reference monitor prioor secoor d0/d7 a0/a6 cs ,ds ,r/w c155p/n c20i f16o master clock pcci pri
MT90401 data sheet 2 zarlink semiconductor inc. the MT90401 can operate in free-run, locked or holdover mode. the loop filter corner frequency can be selected to suit sonet applications or to suit sdh applications. the MT90401 uses an external 20 mhz oscillator as its master clock and it does not require external loop filter components. in hardware mode, the MT90401 can be controlled and monitored via external pins. in microport mode, a microprocessor can be used for more comprehensive control and monitoring. figure 2 - pin connections 80 pin lqfp for MT90401 MT90401ab 40 42 44 46 48 50 52 54 56 58 60 22 24 26 28 30 34 36 38 32 62 80 78 76 74 72 68 66 64 70 20 18 16 14 12 10 8 6 4 2 tdi tc lk tms tdo vref vss4 pri sec e3/ds3 e3ds3/oc3 c155p c155n vdd vdd2 vss3 ic vss2 fs1 trst fs2 ms1 a2 a1 c4o c8o c16o f16o vss1 vdd1 sonet/sdh a5 f0o c2o ic a3 a4 ms2 vss9 a6 f8o secoor oe cs rst hw d1 d2 d3 vss8 ic d6 r/w ic vdd5 d4 d5 d7 ic a0 c1.5o c19o rsel tclr vdd3 nc c20i c34/c44 vss7 vdd4 holdover pcci lock flock ds ic prioor vss5 ic c6o d0
MT90401 data sheet 3 zarlink semiconductor inc. pin description pin # name description 1ic internal connection . leave unconnected. 2-5 a1 - a4 address 1 to 4 (5 v tolerant inputs). address inputs for the parallel processor interface. 6v ss9 digital ground. 0 volts 7, 8 a5, a6 address 5, to 6 (5 v tolerant input). address inputs for the parallel processor interface. 9sonet/sd h sonet/sdh (input). in hardware mode set this pin high to have a loop filter corner frequency of 70 millihertz and limit the phase slop e to 885 ns per second. set this pin low to have a corner frequency of approximately 1. 1 hertz and limit the phase slope to 53 ns per 1.326 ms. this pin performs no function if the device is not in hardware mode. 10 v dd1 positive power supply. digital supply. 11 v ss1 digital ground. 0 volts 12 f16o frame pulse st-bus 8.192 mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st- bus operation at 8.192 mb/s. 13 c16o clock 16.384 mhz (cmos output). this output is used for st-bus operation with a 16.384 mhz clock. 14 c8o clock 8.192 mhz (cmos output). this output is used for st-bus operation at 8.192 mb/s. 15 c4o clock 4.096 mhz (cmos output). this output is used for st-bus operation at 2.048 mb/s and 4.096 mb/s. 16 c2o clock 2.048 mhz (cmos output). this output is used for st-bus operation at 2.048 mb/s. 17 f0o frame pulse st-bus 2.048 mb/s (cmos output). this is an 8 khz 244 ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st- bus operation at 2.048 mb/s and 4.096 mb/s. 18 ms1 mode/control select 1 (input). this input, together with ms2, determines the state (normal, holdover, or freerun) of operation. see table 3 on page 15. the logic level at this input is gated in by the rising edge of f8o. this pin performs no function if the device is not in hardware mode. 19 ms2 mode/control select 2 (input). this input, together with ms1, determines the state (normal, holdover or freerun) of operation. see table 3 on page 15. the logic level at this input is gated in by the rising edge of f8o. this pin performs no function if the device is not in hardware mode. 20 f8o frame pulse generic (cmos output). this is an 8 khz 122 ns active high framing pulse, which marks the beginning of a tdm frame. this is typically used for tdm streams operating at 8.192 mb/s. 21 e3ds3/oc3 e3ds3 or oc-3 selection (input). in hardware mode a low on this pin enables the differential 155.52 mhz output clock on the c155n/c155p pins; this will also cause the c34/c44 pin to output its nominal clock frequ ency divided by 4. in hardware mode, a high on this pin disables the di fferential 155.52 mhz output cl ock on the c155n/c155p pins; this will also cause the c34/ c44 pin to output its nominal clo ck frequency. this pin performs no function if the device is not in hardware mode.
MT90401 data sheet 4 zarlink semiconductor inc. 22 e3/ds3 e3 or ds3 selection (input). in hardware mode a low on this pin selects a clock rate of 44.736 mhz for the c34/c44 pin, while a high se lects a clock rate of 34.368 mhz. this pin performs no function if the device is not in hardware mode. 23 sec secondary reference (input). this is one of two (pri & sec) input reference sources (falling edge) used for synchronization. one of four possible frequencies ( 8khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) may be used . in hardware mode the selection of the input reference is based upon the ms1, ms2 and rsel control inputs. 24 pri primary reference (input). this is one of two (pri & sec) input reference sources (falling edge) used for synchronization. one of four possible frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) may be used . in hardware mode the selection of the input reference is based upon the ms1, ms2 and rsel control inputs. 25 v ss2 digital ground. 0 volts 26 ic internal connection. leave unconnected 27 v ss3 analog ground. 0 volts 28 v dd2 positive analog power supply. analog supply. 29 v dd positive power supply. digital supply. 30 31 c155n, c155p lvds 155.52 mhz (output)). differential outputs generating a 155.52 mhz clock 32 v ss4 digital ground. 0 volts 33 vref lvds reference voltage (input). 34 tdo ieee 1149.1a test data output (output). if not used, this pin should be left unconnected. 35 tms ieee 1149.1a test mode selection (input) . if not used, this pin should be pulled high. 36 tclk ieee 1149.1a test clock signal (input) . if not used, this pin should be pulled high. 37 trst ieee 1149.1a reset signal (input). if not used, this pin should be held low. 38 tdi ieee 1149.1a test data input (input). if not used, this pin should be pulled high. 39 fs2 frequency select 2 (input). this input, in conjunction wi th fs1, selects which of four possible frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) may be input to the pri and sec inputs. for more details see fs2 bit description in table 6 - control register 1 (address 00h - read/write). 40 fs1 frequency select 1 (input). this input, in conjunction wi th fs2, selects which of four possible frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) may be input to the pri and sec inputs. for more details see fs1 bit description in table 6 - control register 1 (address 00h - read/write). 41 prioor primary reference out of range (cmos output). a logic high at th is pin indicates that the primary reference is off the pll center frequency by more than 12 ppm. the measurement is done on a 1 second basis us ing a signal derived fr om the 20 mhz clock input on c20i. when the accuracy of the 20 mhz clock is 4.6 ppm, the effective out of range limits of the prioor signal will be + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. 42 c1.5o clock 1.544 mhz (cmos output). this output is used in t1 applications. 43 c6 clock 6.312 mhz (cmos output). this output is used for ds2 or j2 applications. 44 ic internal connection. tie low for normal operation. pin description (continued) pin # name description
MT90401 data sheet 5 zarlink semiconductor inc. 45 v ss5 digital ground. 0 volts 46 c19o clock 19.44 mhz (cmos output). this output is used in oc-n and stm-n applications. 47 rsel reference source select (input). a logic low selects the pri (primary) reference source as the input reference signal and a logic high selects the sec (secondar y) input. the logic level at this input is gated in by the rising edge of f8o. for more details see rsel bit description in table 6 - control regi ster 1 (address 00h - read/write). 48 tclr tie circuit clear (input). a logic low at this input clears the time interval error (tie) correction circuit resulting in a realignment of output phase with input phase. the tclr pin should be held low for a minimum of 300 ns. when th is pin is held low, the time interval error correction circuit is disabled. 49 v dd3 positive power supply. digital supply . 50 nc no connection. 51 c20i 20 mhz clock input (5 v tolerant input). this pin is the input for the master 20 mhz clock. 52 v ss7 digital ground. 0volts 53 c34/c44 controlled clock 34.368 mhz / clock 44.736 mhz (cmos output). this output clock is programmable to be either 34.368 mhz (for e3 applications) or 44.736 mhz (for ds3 applications). the output clock is controlled vi a control pins in hardware mode or control bits when the device is in microport mode. if the e3ds3/oc3 control pin or control bit is high, the c34/c44 pin will output its nominal frequency. if the e3ds3/oc3 control pin or bit is low, the c34/c44 pin will output its nominal frequency divided by 4. (c8.5o/c11o) 54 v dd4 positive power supply. digital supply. 55 holdover holdover (cmos output). this output goes high when the device is in holdover mode. 56 pcci phase continuity control input (3 v input). the signal at this pin affects the state changes between primary holdover mode and pr imary normal mode and primary holdover mode and secondary normal mode. the logic leve l at this input is gated by the rising edge of f8o. see figure 12, ?control state diagram? on page 21 for details. 57 lock lock indicator (cmos output). this output goes high when the pll is in frequency lock to the input reference. 58 flock fast lock mode (input). in hardware mode, hold this pin high to lock faster than normal to the input reference. this pin performs no func tion if the device is not in hardware mode. in fast lock mode, the wander generation of the pll is, of necessity, compromised. 59 ds data strobe (5 v tolerant input) . this input is the active low data strobe of the motorola processor interface. 60 ic internal connection. tie low for normal operation. 61 secoor secondary reference out of capture range (cmos output). a logic high at this pin indicates that the secondary reference is off the pll center frequency by more than 12 ppm. the measurement is done on a 1 second basis using a signal derived from the 20 mhz clock input on the c20i pin. when the accuracy of the 20 mhz clock is 4.6 ppm the effective out of range limits of the secoor signal will be + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. pin description (continued) pin # name description
MT90401 data sheet 6 zarlink semiconductor inc. 62 oe output enable (input) . tie high for normal operation. ti e low to force output clocks pins f16 , f8 , c16 , c8, c4 , c2 to a high impedance state. 63 cs chip select (5 v tolerant input) . this active low input enables the non-multiplexed motorola parallel microprocessor interface of the MT90401. when cs is set to high, the microprocessor interface is id le and all bus i/o pins will be in a high impedance state. 64 rst reset (5 v tolerant input). this active low input puts the MT90401 in a reset condition. rst should be set to high for normal operation. the MT90401 should be reset after power- up and after the selected reference frequency is changed. the rst pin must be held low for a minimum of 1msec. to reset the device properly. 65 hw hardware mode (input) . if this pin is tied low, the device is in microport mode and is controlled via the microport. if it is tied high, the device is in hardware mode and is controlled via the control pins ms1, ms2, fs1, fs2, flock and sonet/sdh . 66-69 d0 - d3 data 0 to data 3 (5 v tolerant three-state i/o) . these signals combined with d4-d7 form the bidirectional data bus of the parallel processor interface (d0 is the least significant bit). 70 v ss8 digital ground. 0 volts. 71 ic internal connection. tie low for normal operation. 72 ic internal connection. tie low for normal operation. 73 v dd5 positive power supply. digital supply. 74-77 d4 - d7 data 4 to data 7 (5 v tolerant three-state i/o). these signals combined with d0-d3 form the bidirectional data bus of the parallel processor interface (d7 is the most significant bit). 78 r/w read/write select (5 v tolerant input). this input controls the direction of the data bus d[0:7] during a microproc essor access. when r/w is high, the parallel processor is reading data from the MT90401. when low, the parallel processor is writing data to the MT90401. 79 a0 address 0 (5 v tolerant input). address input for the parallel processor interface. a0 is the least significant input. 80 ic internal connection. tie low for normal operation. pin description (continued) pin # name description
MT90401 data sheet table of contents 7 zarlink semiconductor inc. 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 reference select mux circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 frequency select mux circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 time interval error (tie) corrector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 digital phase lock loop (dpll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 output interface circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 input impairment monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.7 state machine control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.8 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 control and mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1 normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.2 holdover mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3 freerun mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4 fast lock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5 transitions from freerun mode or hold over mode to normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.0 MT90401 measures of performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 jitter generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 jitter tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 jitter transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 frequency accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 holdover accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.6 capture range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 lock range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.8 phase slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 frequency slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.10 time interval error (tie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 maximum time interval error (mtie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12 phase continuity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 phase lock time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.0 MT90401 and network specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.1 master clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.2 tie correction (using pcci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.3 c155 clock generation and lvds output drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4 microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5 output phase adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MT90401 data sheet list of figures 8 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections 80 pin lqfp for MT90401 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3 - tie corrector circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4 - dpll block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 - output interface circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 6 - control state machine block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7 - jitter tolerance gr-1244 1.544 mhz reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8 - jitter tolerance itu-t g.813 option 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9 - jitter tolerance sonet category ii (oc1) 19.44 mhz in put reference. . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10 - jitter and wander transfer with sonet filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11 - jitter and wander transfer with sdh filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12 - control state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13 - lvds voltage offset vos generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14 - timing parameter measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 15 - microport timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 16 - input to output timing for t1/e1 signals (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17 - input to output timing for 19.44 mhz signal (normal mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 18 - output timing 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19 - output timing 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 20 - input controls setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 21 - output timing 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
MT90401 data sheet list of tables 9 zarlink semiconductor inc. table 1 - frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2 - input reference selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 - operating modes and states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4 - control state table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5 - register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 6 - control register 1 (address 00h - read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7 - status register 1 (address 01h - read only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 8 - control register 2 (address 04h - read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9 - set delay word 2 (address 06h - read/write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10 - set delay word 1 (address 07h - read/write). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11 - identification word (address 0fh - read only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MT90401 data sheet 10 zarlink semiconductor inc. 1.0 functional description the MT90401 is a sonet/sdh system synchronizer, providing timing (clock) and synchronization (frame) signals to interface circuits for digital telecommunications trans mission links. figure 1 is a fu nctional block diagram which is described in the following sections. 1.1 reference select mux circuit the MT90401 accepts two simultaneous reference input signal s and operates on their falling edges. either the primary reference (pri) signal or the secondary reference (sec) signal can be selected as input to the tie corrector circuit. the selection is based on the control, mode and reference selection of the device. see table 1 and table 4. 1.2 frequency select mux circuit the MT90401 operates with one of four possible input reference frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz). the frequency select inputs, fs1 and fs2, whic h come from pins in hardware mode and control bits in microport mode determine which of the four frequencies may be used at the reference inputs (pri and sec). both inputs must have the same frequency applied to them. a reset (rst ) must be performed after every frequency select input change. see table 1 - input frequency selection. 1.3 time interval error (tie) corrector circuit the tie corrector circuit, when enabl ed, prevents a step change in phase on the input reference signals (pri or sec) from causing a step change in phase at the input of the dpll block of figure 1. during reference input rearrangement, su ch as during a switch from the prim ary reference (pri) to the secondary reference (sec), a step change in phase on the i nput signals will occur. a phase st ep at the input of the dpll would lead to unacceptable phase changes in the output signal. as shown in figure 3, the tie correcto r circuit receives one of the two refe rence (pri or sec) signals, passes the signal through a programmable delay line, and uses this de layed signal as an internal virtual reference, which is input to the dpll. therefore, the virtual reference is a delayed version of the selected reference. during a switch from one reference to the other, the state machine first changes the mode of the device from normal to holdover. in holdover mode, the dpll no longer uses the virtual refe rence signal, but generates an accurate clock signal using storage techniques. the compare circuit then measures the phase delay between the current phase (feedback signal) and the phase of the new refer ence signal. this delay value is passed to the programmable delay circuit (see figure 3). the new virtual reference signal is now at the same phase position as the previous reference signal would have been if the reference switch had not taken place. the state machine then returns the device to normal mode. fs2 fs1 input frequency 0019.44mhz see fs2 and fs1 bit description in table 6 - control register 1 (address 00h - read/write) 018khz 1 0 1.544 mhz 1 1 2.048 mhz table 1 - frequency selection
MT90401 data sheet 11 zarlink semiconductor inc. figure 3 - tie corrector circuit the dpll now uses the new virtual reference signal, and sinc e no phase step took place at the input of the dpll, no phase step occurs at the output of the dpll. in other words, reference switching will not create a phase change at the input of the dpll, or at the output of the dpll. since internal delay circuitry maintains the alignment between the old virtual reference and the new virtual reference, a phase error may exist between the selected input reference signal and the output signal of the dpll. this phase error is a function of t he difference in phase between the two in put reference signals during reference rearrangements. each time a reference switch is made, the delay between input sign al and output signal will change. the value of this delay is the accumulation of the error measured during each reference switch. the programmable delay circuit can be reset to zero by applying a logic low pulse to the tie circuit clear (tclr ) pin. a minimum reset pulse width is 300 ns. this results in a phase realignment between the input reference signal and the output signal as shown in figur e 16. the speed of the phase alignment correction is limited to 885 ns/s in sonet mode and 53 ns per 1.326 ms in sdh mode, convergence is in the direction of least phase travel. the state diagram of figure 12 indica tes the state changes for which the tie corrector circuit is activated. programmable delay circuit control signal delay value tclr resets delay compare circuit tie corrector enable from state machine control circuit feedback signal from frequency select mux pri or sec from reference select mux virtual reference to dpll
MT90401 data sheet 12 zarlink semiconductor inc. 1.4 digital phase lock loop (dpll) as shown in figure 4, the dpll of the MT90401 consists of a phase detector, phase slope limiter, loop filter, digitally controlled oscillator, and a control circuit. figure 4 - dpll block diagram phase detector - the phase detector compares the virtual refer ence signal from the tie corrector circuit with the feedback signal from the frequency sele ct mux circuit, and provides an error signal corresponding to the phase difference between the two. this error signal is pass ed to the phase slope limiter circuit. the frequency select mux allows the proper feedback signa l to be externally selected (e.g., 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz). phase slope limiter - the phase slope limiter receives the error signal from the phase detector and ensures that the dpll responds to all input transi ent conditions with a limited outp ut phase slope. in sonet mode the maximum output phase slope is limited to 885 ns/s as per telcordia gr-253-core. in sdh mode the maximum output phase slope is 53 ns per 1.326 ms. loop filter - the loop filter is a low pass filter, that defines the network jitter and wander transfer requirements for all input reference frequencies (8 khz, 1.544 mhz, 2.048 m hz, or 19.44 mhz). in sonet mode the loop filter has a cut-off frequency of 70 mhz to comply with telcordi a gr-253-core and gr-1244-core. in sdh mode the loop filter has a cut-off frequency of 1.1hz to comply with itu-t g.813 option 1 and gr-1244-core. control circuit - the control circuit uses status and contro l information from the state machine and the input impairment circuit to set the mode of the dpll. th e three possible modes are normal, holdover and freerun. digitally controlled oscillator (dco) - the dco receives the limited and filt ered signal from the loop filter, and based on its value, generates a corresponding digital output signal. the synchroniza tion method of the dco is dependent on the state of the MT90401. in normal mode, the dco provides an output signal which is frequency and phase locked to the selected input reference signal. in holdover mode, the dco is free running at a fr equency equal to the last locked frequency the dco was generating while in normal mode. in order to improve ac curacy of the holdover mode the actual frequency sample is taken 30 to 60 ms before switching into holdover. in freerun mode, the dco is free running with an accu racy equal to the accuracy of the c20i 20 mhz source. telcordia gr-253-core requires that , during recovery from holdover, sonet clocks not change their output frequency at a rate faster than 2.9 ppm per second. in sonet mode the MT90401 limits the rate of change of its output frequency (frequency slope) to less than 1.9ppm per second; this limit remains in place when the pll is in fast lock mode. control circuit state select from input impairment monitor state select from state machine feedback signal from frequency select mux dpll reference to output interface circuit virtual reference from tie corrector phase slope limiter loop filter digitally controlled oscillator phase detector
MT90401 data sheet 13 zarlink semiconductor inc. lock indicator - if the pll is in frequency lock (frequency lock me ans the center frequency of the pll is identical to the line frequency), and the input phase offset is sma ll enough such that no phase slope limiting is exhibited, then the lock signal will be set high. 1.5 output interface circuit the output of the dco (dpll) is used by the output interf ace circuit to provide the output signals shown in figure 5. the output interface circuit uses five tapped delay lines in MT90401 followed by a t1 divider circuit, an e1 divider circuit, a ds2 divider ci rcuit, and a x4/x8 pll, to generate the required output signals. five tapped delay lines are used to generate 8.592 mh z, 11.184 mhz, 16.384 mhz, 12.352 mhz, 12.624 mhz and 19.44 mhz signals. the e1 divider circuit uses the 16.384 mhz signal to ge nerate four clock outputs and three frame pulse outputs. the c8o, c4o and c2o clocks are generated by simply dividing the c16o clock by two, four and eight respectively. these outputs have a nominal 50% duty cycle. the frame pulse outputs (f0o , f8o, and f16o ) are generated directly from the c16 clock. the t1 divider circuit uses the 12.352 mhz signal to gener ate c1.5o. this output has a nominal 50% duty cycle. the ds2 divider circuit uses the 12. 624 mhz signal to generate the clock out put c6o. this output has a nominal 50% duty cycle. the 19.44 mhz signal is output on the c19o pin and it is multiplied by an internal pll to generate the 155.52 mhz clock output on the c155p/n pins. the c155 p/n clock has a nominal 50% duty cycle. the 8.592 mhz and 11.184 mhz signals are multiplied by an internal pll to generate the 34.368 mhz or 44.736 mhz clock output on the c34/c44 pin. if the internal pll is dedicated to the c155p/n clock then the c34/c44 pin will output the 8.592 mhz or 11.184 mh z clocks. the 34.368 mhz and 44.736 mhz clocks have a nominal 50% duty cycle. the duty cycles of the 8.59 2 mhz and 11.184 mhz signals are dependent on the duty cycle of the 20 mhz clock input to the c20i pin.
MT90401 data sheet 14 zarlink semiconductor inc. figure 5 - output interf ace circuit block diagram the t1 and e1 signals are generated from a common dpll signal. consequently, all frame pulses and clock outputs are locked to one another for all operating states , and are also locked to the selected input reference in normal mode. see figure 18. all frame pulses and clock outputs have limited driving capability, and should be buffered when driving capacitive loads exceeding 30 pf. 1.6 input impairment monitor this circuit monitors the input signal to the dpll a nd automatically enables the auto -holdover when the frequency of the incoming signal is outside the auto-holdover c apture range. (see performance characteristics - mode switching). this includes a complete loss of incoming si gnal, or a large frequency shift in the incoming signal. when the incoming signal returns to normal, the dpll is retu rned to normal mode with t he output signal locked to the input signal. the holdover output signa l in the MT90401 is based on the incoming signal 30 ms (minimum) to 60 ms prior to entering the holdover mode. the amount of phase dr ift while in holdover is negligible because the holdover mode is very accurate (i.e., 0.02 ppm). consequently, th e phase delay between the input and output after switching back to normal mode is preserved. tapped delay line from dpll t1 divider e1 divider 16mhz 12mhz c1.5o c2o c4o c8o c16o f0o f8o f16o tapped delay line tapped delay line x4 / x8 pll 12mhz 19mhz c155p/n c19o ds2 divider c6o tapped delay line c34/c44 8.5/11.2mhz tapped delay line
MT90401 data sheet 15 zarlink semiconductor inc. 1.7 state machine control an internal state machine can be enabled to control the tie corrector circuit as show n in figure 1. in hardware mode, control is based on the logic levels at the cont rol inputs rsel, ms1, ms2 and pcci (see figure 6). in microport mode, control is based on the state of c ontrol bits rsel, ms1 and ms2 and the pcci pin. when switching from primary holdover to primary normal, the tie corrector circuit is enabled when pcci = 1, and disabled when pcci = 0. all state machine changes occur synchronously on the ri sing edge of f8o. see the control and mode of operation section for full details. figure 6 - control state machine block diagram 1.8 master clock the MT90401 uses an external oscillator as the master timing source. for recommend ed master timing circuits, see the applications - master clock section. 2.0 control and mode of operation the MT90401 has three possible modes of operation, normal, holdover and freerun. in hardware mode the mode/control select pins ms2 and ms 1 select the mode and method of control as shown in table 3. the active reference input (pri or sec) is selected by the rsel pin as shown in table 2. refer to table 4 and figure 12 for details of the state change sequences. rsel input reference 0pri 1 sec table 2 - input reference selection ms2 ms1 mode 0 0 normal 0 1 holdover 1 0 freerun 11 reserved table 3 - operating modes and states ms1 ms2 to reference select mux to tie corrector enable control state machine to dpll state select pcci rsel
MT90401 data sheet 16 zarlink semiconductor inc. 2.1 normal mode normal mode is typically used when a slave clock source, synchronized to the network is required. in normal mode, the MT90401 provides timing and frame synchronization signals, whic h are synchronized to one of two reference inputs (pri or sec). the input re ference signal may have a nominal frequency of 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz. the selection of input references is control dependent as shown in state table 4. the reference frequencies are selected by the frequency control pins/b its fs2 and fs1 as shown in table 1. 2.2 holdover mode holdover mode is typically used when network synchronization is temporarily disrupted. in holdover mode, the MT90401 provides timing and synchr onization signals, which are not locked to an external reference signal, but are based on st orage techniques. the storage value is determined while the device is in normal mode and locked to an external reference signal when in normal mode, and locked to the input reference signal, a numer ical value corresponding to the MT90401 output reference frequency is stored al ternately in two memory locations ev ery 30 ms. when the device is switched into holdover mode, the value in memory from between 30 ms and 60 ms is used to set the output frequency of the device. the frequency accuracy of holdover mode is 0.02 ppm, which translates to a worst case 14 frame (125 us) slips in 24 hours. this is better than the telcor dia gr-1244-core stratum 3 requirement of 0.37 ppm (255 frame slips per 24 hours). two factors affect the accuracy of holdover mode. one is drift on the master clock and the other is jitter on the reference signal. the drift on the mast er clock oscillator propagat es unattenuated an d causes the same drift on the output clocks. this drift can only be reduced by selecti ng more stable master clock oscillator. for example, a 4.6 ppm temperature compensated clock oscillator may hav e a temperature coefficien t of 0.03 ppm per degree c. the 10 degc change wh ile in holdover mode, will result in an additi onal offset in freque ncy accuracy equal to 0.3ppm which is much greater t han the internal holdover accuracy of the MT90401 (0.02 ppm). the other factor affecting accuracy is large jitter on the reference input prior (30 ms to 60 ms) to the mode switch. for instance, jitter of 7.5 ui at 700 hz may reduce th e holdover mode accuracy from 0.02 ppm to 0.10 ppm. 2.3 freerun mode freerun mode is typically used when a master clock sour ce is required, or immediately following system power-up before network synchronization is achieved. in freeru n mode, the MT90401 provides timing and synchronization signals which are based on the master clock frequency (c20i) only, and are not synchronized to the reference signals (pri and sec). the accuracy of the output clock is equal to t he accuracy of the master clock (c20i). so if a 20 ppm output clock is required, the master clock must also be 20 ppm. see applications - master clock section. 2.4 fast lock mode fast lock mode is a submode of normal mode, it is used to allow the MT90401 to lock to a reference eight times more quickly than normal. fast lock mode necessarily co mpromises the wander generation characteristics of the MT90401. when the MT90401 is in fast lock mode and sonet mode at the same time, the pll frequency slope is limited to less than 1.9 ppm per second.
MT90401 data sheet 17 zarlink semiconductor inc. 2.5 transitions from freerun mode or holdover mode to normal mode telcordia gr-253-core requires sonet internal clocks to settle within 100 s after transitioning from freerun mode or holdover mode to normal mode. during such a transition, the wander filtering requirements for a sonet internal clock are relaxed to make a 100 s settling time possible. to meet the gr-253-core 100 s settling time requirement at power-up and during a transition from freerun mode to normal mode the MT90401 should be placed in its sdh mode until lock is achieved. when the pll indicates lock the MT90401 should be placed in sonet mode. during a transition from holdover mode to normal m ode, gr-253-core requires a sonet internal clock to limit the frequency slope to less than 2.9 ppm per second. to meet the 100 s settlin g time during such a transition it is necessary to keep the MT90401 in sonet mode and fast lock mode until lock is achieved. when the pll indicates lock the MT90401 can be taken out of its fast lock mode. a transition from holdover mode to norm al mode can result in a large initial frequency offset, for example 4.6 ppm, between the clock?s reference and its output. the 2.9 ppm per second frequency slope limit required by gr-253-core places a lower limit on the time it takes for a sonet internal clock to acquire a new frequency. while the clock is acquiring the new frequency a phase error will accumulate which could cause the clock?s settling time to be longer than 100 s. gr-1244-core and gr-253-co re allow a clock to ignore some of the phase error accumulated during the transition fr om holdover mode to normal mode. during a transition from holdover mode to normal mode, if the MT90401 has not achieved lock within 16 seconds, it is recommended that the pll be put br iefly into its holdover mode and then returned to normal mode by toggling the ms1 pin or the ms1 control bit. toggling the pll into and out of ho ldover will clear any accumulated phase error and reduce the settling time. 3.0 MT90401 measures of performance the following are some synchronizer performance indicators and their corr esponding definitions. 3.1 jitter generation jitter generation is the amount of jitter produced by a pll and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the devic e, and measuring its output jitter. jitter generation may also be measured when the device is in a non-synchronizing m ode, such as free running or holdover, by measuring the output jitter of the device. jitter generation is usually m easured with various band-limiting filters depending on the applicable standards. 3.2 jitter tolerance jitter tolerance is a measure of the ability of a pll to oper ate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter frequencie s) when jitter is applied to its reference. the applied jitter magnitude and jitter frequency depends on the ap plicable standards (see figures 7, 8 and 9).
MT90401 data sheet 18 zarlink semiconductor inc. figure 7 - jitter tolerance gr-1244 1.544 mhz reference figure 8 - jitter tolera nce itu-t g.813 option 1 figure 9 - jitter tolerance sonet cate gory ii (oc1) 19.44 mhz input reference 3.3 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. i nput jitter is applied at va rious amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. for the MT90401, two internal elements determine the jitter attenuation. this includes the low pass loop filter and the phase slope limiter. both of these parameters have different settings depending on whether the device is in
MT90401 data sheet 19 zarlink semiconductor inc. sonet or sdh mode. for sonet mode the loop filter has a corner frequency of 70 millihertz and the output phase slope is limited to 885 ns per second. for sdh mode t he loop filter has a corner frequency of 1.1 hertz and a maximum phase slope of 53 ns per 1.326 milliseconds. if th e input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited. the MT90401 has ten outputs that can be locked to four pos sible input frequencies for a total of 40 possible jitter transfer functions. since all outputs are derived from the same internal signal , the jitter transfer values for the four cases, 8 khz to 8 khz, 1.544 mhz to 1.544 mhz, 2.048 mhz to 2.048 mhz 19.44 mhz to 19.44 mhz can be applied to all outputs. figure 10 - jitter and wander transfer with sonet filter figure 11 - jitter and wander transfer with sdh filter it should be noted that 1 ui at 1.544 mhz is 648 ns, which is not equal to 1 ui at 2.048 mhz, which is 488 ns. consequently, a transfer value using different input and ou tput frequencies must be calculated in common units (e.g., seconds) as shown in the following example. example: what is the t1 and e1 output jitter when the t1 input jitter is 20ui (t1 ui units) and the t1 to t1 jitter attenuation is 18 db?
MT90401 data sheet 20 zarlink semiconductor inc. using the above method, the jitter attenuation can be calcul ated for all combinations of inputs and outputs based on the four jitter transfer functions provided. since intrinsic jitter generation is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. consequently, accurate ji tter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). description state input controls freerun normal (pri) normal (sec) holdover (pri) holdover (sec) ms2 ms1 rsel pcci s0 s1 s2 s1h s2h 0 0 0 0 s1 - s1 mtie s1 s1 mtie 0 0 0 1 s1 - s1 mtie s1 mtie s1 mtie 0 0 1 x s2 s2 mtie - s2 mtie s2 mtie 01 0 x / s1h / / 01 1 x / s2h s2h / - 10 x x - s0 s0 s0 s0 legend: - no change / not valid mtie state change occurs with tie corrector circuit refer to control state diagram for state changes to and from auto-holdover state table 4 - control state table outputt1 inputt1 a ? 20 ------ ?? ?? 10 = outputt1 20 18 ? 20 -------- - ?? ?? 10 2.5ui t1 () == outpute1 outputt1 644ns () 488ns () ------------------- 3.3ui t1 () = = outpute1 outputt1 1uit1 () 1uie1 () --------------------- - =
MT90401 data sheet 21 zarlink semiconductor inc. figure 12 - control state diagram 3.4 frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mo de. for the MT90401, the freerun accuracy is equal to the master clock (c20i) accuracy. 3.5 holdover accuracy holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techni ques. for the MT90401, the storage value is determined while the device is in normal mode and locked to an exte rnal reference signal. the in itial frequency offset of the MT90401 in holdover mode is + 20 x 10 -9 . this is more accurate than telcordia?s gr-1244-core stratum 3 requirements of + 50 x 10 -9 . once the MT90401 has transitioned into holdover mode, holdover stability is determined by the stability of t he 20 mhz master clock oscillator. the absolute master clock (c20i) accuracy of the mt9040 1 does not affect holdover accuracy, but the change in c20i accuracy while in holdover mode does. phase re-alignment phase continuity maintained ( without tie corrector circuit) phase continuity maintained (with tie corrector circuit) notes: (xxx) ms2 ms1 rsel {a} invalid reference signal movement to normal state from any state requires a valid input signal {a {a} s0 freerun (10x) s2h holdover secondary (011) s1h holdover primary (010) s2 normal secondary (001) s1 normal primary (000) (pcci=0) (pcci=1) s1a auto-holdover primary s2a auto-holdover secondary pcci-0 pcci-1 in the case where 19.44 mhz input reference clocks are selected (fs2,fs1 = 00) the MT90401 may latch inaccurate phase reading during transition between states: s1a>>s1 and s2a>>s2 which may cause frequency step exceeding 4.6 ppm and longer than 100 sec lock time.
MT90401 data sheet 22 zarlink semiconductor inc. 3.6 capture range also referred to as pull-in range. this is the input fr equency range over which the sync hronizer must be able to pull into synchronization. the MT90401 capture range is equal to 52 ppm minus the accuracy of the master clock (c20i). for example, a 32 ppm master clock results in a capture range of 20 ppm. MT90401 provides two pins and two bits, prioor and sec oor, to indicate whether the primary and secondary reference are within the 12 ppm of the nominal frequency. when the accuracy of the 20 mhz oscillator is 4.6 ppm the effective out of range limits of the prioor and secoor pins will be +16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. both references are monitored at the sa me time. prioor and secoor are updated every 1.0 to 1.5 seconds. 3.7 lock range this is the input frequency range over which the synchronizer must be able to maintain synchronization. the lock range is equal to the capture range for the MT90401. 3.8 phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal. the given signal is typically the output signal. an ideal signal is one t hat is at exactly the nominal frequency and is completely free of jitter and wander. 3.9 frequency slope frequency slope is measured in ppm per second and is the ra te at which the fractional frequency offset of a given signal changes. the fractional frequency offset is calcul ated with respect to an idea l signal. the given signal is typically the output signal. an ideal signal is one that is at exactly the nominal frequency and is completely free of jitter and wander. 3.10 time interval error (tie) tie is the time delay between a given ti ming signal and an ideal timing signal. 3.11 maximum time interval error (mtie) mtie is the maximum peak to peak delay between a give n timing signal and an ideal timing signal within a particular observation period. 3.12 phase continuity phase continuity is the phase difference between a given timi ng signal and an ideal timing signal at the end of a particular observation period. usually, the given timing signal and the ideal timing signal are of the same frequency. phase continuity applies to th e output of the synchronizer after a signal disturbance due to a reference switch or a mode change. mtie s () tiemax t () tiemin t () ? =
MT90401 data sheet 23 zarlink semiconductor inc. 3.13 phase lock time this is the time it takes the synchronizer to phase lock to the input signal. phase lock occurs when the input signal and output signal are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors which include: 1. initial input to output phase difference 2. initial input to output frequency difference 3. synchronizer loop filter 4. synchronizer limiter although a short lock time is desirable, it is not always possible to achiev e due to other synchronizer requirements. for instance, better jitter transfer performance is achi eved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope per formance (limiter) results in longer lock times. the MT90401 loop filter and limiter were optimized to meet the gr-253-core, gr -1244-core, and g-813 jitter transfer and phase slope requirements. 4.0 MT90401 and network specifications the MT90401 meets all applicable pll require ments for the following specifications. 1. telcordia gr-1244-core december 2000 for stratum 3, sonet minimum clock (smc), stratum 4 enhanced and stratum 4 2. telcordia gr-253-core september 2000 for sonet internal clocks 3. ansi t1.101 (ds1) february 1994 for stratum 3, stratum 4 enhanced and stratum 4 4. ansi t1.105.09-1996 for so net minimum clocks (smcs) 5. itu-t g.813 august 1996 for option1 and opti on 2 clocks (with external jitter attenuator) 5.0 applications this section contains MT90401 application specific details for master clock operation, lvds output drivers setup, microport functionality and ou tput clock phase adjustment. 5.1 master clock in freerun mode, the frequency tolerance at the clock outputs is identical to the frequency tolerance of the source at the c20i input pin. another consideration in determining t he accuracy of the master timing sour ce is the desired capture range. the sum of the accuracy of the master timing source and the capt ure range of the MT90401 will always equal 52 ppm. for example, if the ma ster timing source is 20 ppm, then the capt ure range will be 32 ppm. 5.2 tie correction (using pcci) when primary holdover mode is entered for short time periods, tie correction should not be enabled. this will prevent unwanted accumulated phase change between the input and output. for example, we can estimate phase accumulation for a case when ten normal to holdover to normal sequential mode changes occur, with each ho ldover entered for 2 s with tie enabled . each mode change could account for a phase shift as large as 250 ns. thus, the accumulated phase could be as large as 2.9 us, and, the overall mtie could be as large as 2.9 us.
MT90401 data sheet 24 zarlink semiconductor inc. ? 0.02 ppm is the accuracy of holdover mode ? 50 ns is the maximum phase continuity of the MT90401 from normal mode to holdover mode ? 200 ns is the maximum phase continuity of the mt 90401 from holdover mode to normal mode (with or without tie corrector circuit) when the same ten normal to holdover to normal mode changes occur with tie disabled , the overall mtie will only be 250 ns. there would be no accumulated phase change, since the input to output phase is re-aligned after every holdover to normal state change. 5.3 c155 clock generati on and lvds output drivers the MT90401 provides a 155.52 mhz clock that is freque ncy locked to the internally generated 19.44 mhz clock. the locking of both clocks is achieved by the internal analog pll that multiplies the 19.44 mhz clock eight times. this c155 clock is output on pins c155p and c155n in lvds format. the lvds offset voltage vos is set by applying an external 1.25 v reference vo ltage to the vref input (pin 33). this pin can be connected to a common 1.25 v voltage reference that may exist on the custom er board or alternatively can be generated by a simple voltage divider as it is shown in figure 13 - lvds volt age offset vos generation circui t. to ensure proper operation of lvds drivers, the decoupling capacitor must be placed very close to the MT90401 package. figure 13 - lvds voltage offset vos generation circuit 5.4 microport if the hw pin is tied low, an 8 bit motorola microprocessor may be used to control the pll and report on the device status. in this case the control pins sonet/sdh, rsel, ms1, ms2, fs1, fs2, and flock are unused and they are replaced by the c ontrol bits sonet/sdh , rsel, ms1, ms2, fs1, fs2, flock. the input pin pcci remains in use. the output pins lock, holdover, secoor, prioor function whether the devic e is in microprocessor mode or hardware mode, but these si gnals are also available in status register 1. the microport provides additional functionality not available in hardware. phase hold 0.02ppm 2s 40ns == phase state 50ns 200ns 250ns = + = phase 10 10 250ns 40ns + () 2.9us ==
MT90401 data sheet 25 zarlink semiconductor inc. 5.5 output phase adjustment two control registers ar e available to program the output phase of fset of the generated clocks. all 16.384 mhz derived outputs clocks, f16o , f80, f0o , c16o , c8o, c4o and c2o can be collectively shifted up to 125 microseconds with a step size of 60 ns with respect to the input reference by programming the set delay word 1 and set delay word 2 registers. control and status registers address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) register read/ write function 00h (table 6) control register 1 read/ write rsel, fs2, fs1, ms2, ms1, sonet/sdh flock, tclr 01h (table 7) status register 1 read only prioor, secoor, lock, holdover, rsv, flim, rsv, rsv 02h reserved read only 03h reserved read only 04h (table 8) control register 2 read/ write e3/ds3/oc3 , e3/ds3 , rsv=0, rsv=0, rsv=0, rsv=0, rsv=0, rsv=0. 05h reserved read /write set all bits to zero. 06h (table 9) set delay word 2 read/ write rsv=0, rsv=0, rsv=0, rsv=0, offen, c16ocnt10,c16ocnt9, c16ocnt8 07h (table 10) set delay word 1 read/ write c16ocnt7-0 08h reserved read/ write set all bits to zero. 09h reserved read only 0ah reserved read only 0bh reserved read only 0ch reserved read only 0dh reserved read only table 5 - register map
MT90401 data sheet 26 zarlink semiconductor inc. 0eh reserved read only 0fh (table 11) identification word read only id7-0 10h reserved read/ write set all bits to zero. bit name functional description 7 rsel reference select . a zero selects the pri (primary) reference source as the input reference signal and a one selects the sec (secondary) reference. switching between reference clocks operating at 8 khz, 1. 544 mhz and 2.048 mhz can be done at any time and without any special setup procedures. howe ver it is recommended that the switching of the 19.44 mhz references will be performed by forcing pll temporary into holdover mode (ms2,ms1=01) to prevent excessive phase accumulation in the internal controller. the pll can be switched back to normal mode (ms2,ms1= 00) 250 us after the new input reference has been selected. 6 - 5 fs2-1 frequency select 2 - 1 . these bits select which of four possible frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) may be input to the pri and sec inputs. fs2 - 0, fs1 - 0 = 19.44 mhz fs2 - 0, fs1 - 1 = 8 khz. fs2 - 1, fs1 - 0 = 1.544 mhz. fs2 - 1, fs1 - 1 = 2.048 mhz. when ?19.44 mhz? reference cl ock option is selected, a lo ss of 19.44 mhz clock or a larger than 30000 ppm frequency deviation ma y create a frequency step exceeding 4.6 ppm upon return from auto-holdover mode. this may result in a lock time that is longer than normally guaranteed. 4 - 3 ms2-1 mode select 2 - 1 : these bits select the pll state of operation. ms2 - 0, ms1 - 0 = normal. ms2 - 0, ms1 - 1 = holdover. ms2 - 1, ms1 - 0 = freerun. ms2 - 1, ms1 - 1 = reserved. 2sonet/sdh sonet / sdh . set to one to move the loop filter corner frequency to 70 millihertz and limit the phase slope to 885 ns per second as per sonet requirements. set to zero to move the corner frequency to 1.1 hz and li mit the phase slope to 53 ns per 1.326 ms. 1flock fast lock . set to one to allow the pll to lock faster than normal to the input reference. during the time that flock is one, the wa nder generation of the pll is, of necessity, compromised. set to zero for normal operation. table 6 - control register 1 (address 00h - read/write) control and status registers (continued) address (a 6 a 5 a 4 a 3 a 2 a 1 a 0 ) register read/ write function table 5 - register map (continued)
MT90401 data sheet 27 zarlink semiconductor inc. 0tclr tie clear . set to zero to clear the time interval error correction circuit resulting in a realignment of output phase with input phase. when this bit is zero, the time interval error correction circuit is disabled. when this bit is one, the time interval error correction circuit will function normally. bit name functional description 7 prioor primary out of range . a one indicates that the primary reference is off the pll center frequency by more than 12 ppm. the measurement is done on a 1 second basis using a signal derived from the 20 mhz clock input on c20i. when the accuracy of the 20 mhz clock is 4.6ppm, the effective out of range limits of the prioor signal will be + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. 6 secoor secondary out of range . a one indicates that the secondary reference is off the pll center frequency by more than 12 ppm. the measurement is done on a 1 second basis using a signal derived from the 20 mhz clock input on c20i. when the accuracy of the 20 mhz clock is 4.6 ppm, the effective out of range limits of the prioor signal will be + 16.6 ppm to -7.4 ppm or +7.4 ppm to -16.6 ppm. 5lock lock . this bit goes high when the pll is in frequency lock to the input reference. 4holdover holdover . this bit goes high whenever the device is in holdover mode. 3rsv reserved. 2flim frequency limit . this bit goes high whenever the reference frequency hits the input frequency offset tolerance of the pll. this bit can flicker high in the event of large excursions of still tolerable input jitter. 1-0 rsv reserved. table 7 - status register 1 (address 01h - read only) bit name functional description 7e3ds3/oc3 e3ds3/oc3 selection. set this bit to zero to enable the differential 155.52 mhz output clock on the c155n/c155p pins an d cause the c34/c44 pin to output its nominal clock frequency divided by 4. set th is bit to one to disable the differential 155.52 mhz output clock on the c155n/c 155p pins and cause the c34/c44 pin to output its nominal clock frequency. 6e3/ds3 e3/ds3. set this bit low to select a clock rate of 44.736 mhz for the c34/c44 pin. set high to select a clock rate of 34.368 mhz for the c34/c44 pins. 5-0 rsv reserved . set to zero for normal operation. table 8 - control register 2 (address 04h - read/write) bit name functional description table 6 - control register 1 (address 00h - read/write) (continued)
MT90401 data sheet 28 zarlink semiconductor inc. bit name functional description 7-4 rsv reserved. set to zero. 3offen offset enable. set high to enable a programmed phase shift between the input reference and the generated clocks. 2 - 0 c16ocnt10-8 c16 offset count. the three most significant bits of the offset delay word. these bits program the offset all clocks derived from 16.384 mhz with respect to the input reference in step sizes of 60 ns. table 9 - set delay word 2 (address 06h - read/write) bit name functional description 7 - 0 c16ocnt 7-0 c16 offset count . the eight least significant bits of the offset delay word. these bits program the offset of all clocks derived from 16.384 mhz with respect to the input reference in step sizes of 60 ns. table 10 - set delay word 1 (address 07h - read/write) bit name functional description 7- 0 id7-0 identification word 7-0 . these bits contain the revision number of the part. table 11 - identification word (address 0fh - read only)
MT90401 data sheet 29 zarlink semiconductor inc. * voltages are with respect to ground (v ss ) unless otherwise stated. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (v ss ) unless otherwise stated. absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v ddr -0.3 7.0 v 2 voltage on any pin v pin -0.3 v dd +0.3 v 3 current on any pin i pin 30 ma 4 storage temperature t st -55 125 c 5 80 lqfp package power dissipation p pd 1000 mw recommended operating conditions* characteristics sym. min. typ. max. units 1 supply voltage v dd 3.0 3.3 3.6 v 2 operating temperature t a -40 25 +85 0 c dc electrical ch aracteristics* characteristics sym. min. ma x. units conditions/notes 1 supply current with c20i = 0v i dds 2 ma outputs unloaded 2 supply current with c20i = 20 mhz i dd 150 ma outputs unloaded 3 cmos high-level input voltage v cih 0.7v dd v 4 cmos low-level input voltage v cil 0.3v dd v 5 input leakage current i il 15 a v i =v dd or 0 v 6 high-level output voltage v oh 2.4 v i oh = 10 ma 7 low-level output voltage v ol 0.4 v i ol = 10 ma 8 lvds differential output voltage v od 250 460 mv z t = 100 w 9 lvds change in v od between complementary output states dv od 40 mv 10 lvds offset voltage v os 1.15 1.35 v 11 lvds change in v os between complementary output states dv os 40 mv 12 lvds output short circuit current i os 20 ma v ci55p = 0 or v c155n = 0 13 lvds output rise/fall times t rf 300 600 ps measured at 20% and 80% * voltages are with respect to ground (v ss ) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions.
MT90401 data sheet 30 zarlink semiconductor inc. * voltages are with respect to ground (v ss ) unless otherwise stated. * supply voltage and operating temperature are as per recommended operating conditions. * timing for input and output signals is based on the worst case figure 14 - timing parameter measurement voltage levels * supply voltage and operating temperature are as per recommended operating conditions. ac electrical characteristi cs - timing parameter measurement voltage levels* characteristics sym. cmos units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v ac electrical characteristi cs - microprocessor timing* characteristics sym. min. m ax. units test conditions 1ds low t dsl 30 ns 2ds high t dsh 30 ns 3cs setup t css 0ns 4r/w setup t rws 18 ns 5address setup t ads 0ns 6cs hold t csh 0ns 7r/w hold t rwh 4ns 8address hold t adh 10 ns 9 data delay read t ddr 50 ns c l =150 pf 10 data hold read t dhr 30 ns 11 data setup write t dsw 0ns 12 data hold write t dhw 10 ns t ir, t or timing reference points all signals v hm v t v lm t if, t of
MT90401 data sheet 31 zarlink semiconductor inc. figure 15 - microport timing figure 16 - input to output timing for t1/e1 signals (normal mode) note: ds and cs may be connected together. ds cs r/w a0-a4 d0-d7 read d0-d7 write t css t rws t ads t csh t rwh t adh valid data t dsw t dhr t ddr t dhw valid data t dsh t dsl v tt v tt v tt v tt v tt v tt, v ct t rw t r15d t r2d t r8d pri/sec 8khz pri/sec 2.048mhz pri/sec 1.544mhz t rw t rw f8o notes: 1. input to output delay values are valid after a tclr or rst with no further state changes
MT90401 data sheet 32 zarlink semiconductor inc. figure 17 - input to output timing for 19.44 mhz signal (normal mode) ac electrical ch aracteristics - output timing* characteristics sym. min. max. units conditions/notes? 1 reference input pulse width high or low (8 khz, 1.544 mhz, 2.048 mhz) t rw 100 ns 2 reference input pulse width high or low (19.4 mhz) t r19w 10 ns 3 reference input rise or fall time t ir, t if 10 ns 4 8 khz reference input to f8o delay t r8d -85 -65 ns 5 1.544 mhz reference input to f8o delay t r15d 400 425 ns 6 2.048 mhz reference input to f8o delay t r2d 220 230 ns 7 19.44 mhz reference input to c19o delay t r19d 38 42 ns 8 f8o to f0o delay t f0d 115 125 ns 9 f8o to f16o delay t f16d 23 35 ns 10 f8o to c1.5o delay t c15d -100 -85 ns 11 f8o to c6o delay t c6d 58 70 ns 12 f8o to c2o delay t c2d -6 5 ns 13 f8o to c4o delay t c4d -6 5 ns 14 f8o to c8o delay t c8d -6 5 ns 15 f8o to c16o delay t c16d -6 5 ns 16 c1.5o pulse width high or low t c15w 315 ns 17 c6o pulse width high or low t c6w 70 ns 18 c2o pulse width high or low t c2w 235 ns 19 c4o pulse width high or low t c4w 115 ns 20 c8o pulse width high or low t c8w 53 ns 21 c16o pulse width high or low t c16w 24 ns 22 c19o pulse width high or low t c19w 9ns 23 c19o to c155 delay t c155d 06ns 24 f0o pulse width low t f0wl 235 250 ns 25 f8o pulse width high t f8wh 115 130 ns c19o pri/sec 19.44mhz t r19d v t v t t r19w t r19w
MT90401 data sheet 33 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 18 - output timing 1 26 f16o pulse width low t f16wl 55 63 ns 27 output clock and frame pulse rise or fall time t or, t of 9ns 28 input controls setup time t s 100 ns 29 input controls hold time t h 100 ns 30 c34o pulse width low or high t c34w 9ns 31 c44o pulse width low or high t c44w 6ns 32 c8.5o pulse width low t c8.5wl 106 ns 33 c11o pulse width low t c11wl 81 ns ac electrical character istics - output timing* (continued) characteristics sym. min. max. units conditions/notes? t f16wl t f8wh t c15w t c15d t c4d t c16d t c8d t f16d t f0d f0o f16o c16o c8o c4o c2o c1.5o t c2d f8o t c4w t f0wl t c16wl t c8w t c2w t c8w t c4w v t v t v t v t v t v t v t v t t c6d t c6w t c6w c6o v t
MT90401 data sheet 34 zarlink semiconductor inc. figure 19 - output timing 2 figure 20 - input controls setup and hold timing figure 21 - output timing 3 c19o v lvh v t c155p c155n v lvl t c19w t c19w t c155d t c155d t h t s f8o ms1,2, rsel, pcci v t v t v t v t v t v t c8.5o c44o c34o t c44w t c11 t c 8.5 c11o
MT90401 data sheet 35 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. * supply voltage and operating temperature are as per recommended operating conditions. ac electrical characteristics - c20i master clock input* characteristics sym. min. ma x. units conditions/notes? 1 duty cycle 40 60 % 2 rise time 10 ns 3 fall time 10 ns performance characteristics: mode switching* characteristics min. typ. m ax. units conditions/notes? 1 holdover mode accuracy with c20i at: 0ppm -0.02 +0.02 ppm 2 20ppm -0.02 +0.02 ppm 3 capture range with c20i at: 0ppm -52 +52 ppm 4 20ppm -32 +32 ppm 5 phase lock time 100 s 4.6 ppm frequency offset 6 output phase continuity with: reference switch 200 ns 7 mode switch to normal 200 ns 8 mode switch to freerun 200 ns 9 mode switch to holdover 50 ns 10 output phase slope - sdh mode - sonet mode 40 885 us/s ns/s 53 ns per 1.326 ms 11 reference input for auto-holdover with: 8khz -30k +30k ppm 12 1.544mhz -30k +30k ppm 13 2.048mhz -30k +30k ppm 14 19.44mhz -30k +30k ppm performance characteris tics: output jitter generation - filtered characteristics max uipp max ns-pp notes 1 intrinsic jitter at c1.5o (1.544 mhz) 0.004 2.76 filter: 10 hz - 40 khz 2 intrinsic jitter at c2o (2.048 mh z) 0.004 1.83 filter: 20 hz - 100 khz 3 intrinsic jitter at c19o (19.44 mhz) 0.100 5.20 filter: 500 hz - 1.3 mhz oc-3 4 intrinsic jitter at c19o (19.44 mhz) 0.100 5.16 filter: 65 khz - 1.3 mhz oc-3 5 intrinsic jitter at c34o (34.368 mhz) 0.044 1.30 filter: 100 hz - 800 khz 6 intrinsic jitter at c34o (34.368 mhz) 0.039 1.15 filter: 10 khz - 800 khz 7 intrinsic jitter at c44o (44.736 mhz) 0.044 0.99 filter: 10 hz - 400 khz 8 intrinsic jitter at c44o (44.736 mhz) 0.037 0.82 filter: 30 khz - 400 khz
MT90401 data sheet 36 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristi cs: output jitter generation - filtered (vdd = 3.3v +/- 10%, ta = -5c to +85c) characteristics max uipp max ns-pp notes 1 intrinsic jitter at c155o (155.52 mhz) 0.12 0.76 filter: 100 hz - 400 khz oc-1 2 intrinsic jitter at c155o (155.52 mh z) 0.11 0.69 filter: 20 khz - 400 khz oc-1 3 intrinsic jitter at c155o (155.52 mhz) 0.18 1.13 filter: 500 hz - 1.3 mhz oc-3 4 intrinsic jitter at c155o (155.52 mhz) 0.13 0.83 filter: 65 khz - 1.3 mhz oc-3 performance characteristi cs: output jitter generation - unfiltered* characteristics sym. max uipp max ns-pp notes 1 intrinsic jitter at c1.5o (1.544 mhz) 0.010 6.5 2 intrinsic jitter at c2o (2.048 mhz) 0.012 5.8 3 intrinsic jitter at c4o (4.096 mhz) 0.027 6.5 4 intrinsic jitter at c6o (6.312 mhz) 0.037 5.8 5 intrinsic jitter at c8o (8.192 mhz) 0.048 5.9 6 intrinsic jitter at c8.5o (8.592 mhz) 0.032 3.8 7 intrinsic jitter at c11o (11.184 mhz) 0.036 3.2 8 intrinsic jitter at c16o (16.384 mhz) 0.096 5.8 9 intrinsic jitter at c19o (19.44 mhz) 0.11 5.6 10 intrinsic jitter at c34o (34.368 mhz) 0.12 3.5 11 intrinsic jitter at c44o (44.736 mhz) 0.12 2.6 12 intrinsic jitter at c155o (155.52 mhz) 0.21 1.3 13 intrinsic jitter at f0o (8 khz) na 4.7 14 intrinsic jitter at f8o (8 khz) na 4.0 15 intrinsic jitter at f16o (8 khz) na 3.1

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